Reduction in system cost and power consumption through the employment of 1.2-V VIO SPI NOR Flash technology
New 2-Voltage SPI NOR Flash Architecture Offers Efficiency and Speed
A new two-voltage SPI NOR flash architecture is making waves in the semiconductor industry, promising to streamline the interface between sub-10-nm SoCs and traditional 1.8-V flash memory. This innovative design offers multiple benefits, including reduced bill of materials (BOM) cost, simplified PCB layout, lower power consumption, faster page programming, and higher data throughput.
The key to this architecture lies in the NOR flash device's ability to use a lower I/O voltage (1.2 V) for interface signaling while maintaining a core operation voltage (1.8 V). This dual-voltage approach eliminates or minimizes the need for level shifters between the SoC and the flash memory, resulting in BOM reduction and PCB simplification. The design reduces the system’s overall component count and cost by removing external components such as level translators, leading to a simpler and smaller board layout.
In terms of power consumption, lowering the I/O voltage directly reduces power during read operations. For example, current consumption in standby modes can drop to around 12 µA, and deep power-down to 200 nA, significantly cutting power usage compared to conventional 1.8-V SPI NOR flash devices.
The dual-voltage SPI NOR solution also boasts improved page programming speed due to optimized voltage levels for faster internal memory operations. A 256-byte page programming time of approximately 0.15 ms is achievable, which is about 40% faster than conventional 1.8-V SPI NOR flash devices. This speed-up enhances write throughput and overall system responsiveness.
Data throughput is another area where the two-voltage system excels. Modern SPI NOR architectures support interfaces like Quad or Octal SPI that increase read bandwidth significantly (up to 400 MB/s), enabling faster system boot and code execution. The two-voltage system can be integrated with these enhanced SPI modes to improve throughput without substantially raising power or complexity.
It is worth noting that pure 1.2-V NOR flash may not be able to handle higher-performance applications that require a two-voltage solution. However, the new architecture offers a viable alternative, with two types of products supporting the 1.2-V SPI NOR flash architecture: pure 1.2-V SPI NOR flash and 1.8-V core voltage with a 1.2-V VIO interface voltage.
In summary, the two-voltage SPI NOR architecture offers a more efficient way to interface sub-10-nm SoCs with traditional 1.8-V flash by reducing the need for voltage level translation, lowering power consumption during reads, speeding up page programming by about 40%, and enabling higher data throughput through advanced SPI modes, all while cutting BOM and simplifying PCB design. This new architecture is poised to play a significant role in emerging market segments such as edge AI, automotive, clean energy, and connectivity, where SoCs built on fabrication process nodes of 10 nm and below are becoming increasingly prevalent.
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